Networks on Chip

B. Gebremichael, F.W. Vaandrager, M. Zhang, K. Goossens, E. Rijpkema and A. Radulescu. Deadlock Prevention in the Aethereal Protocol. In D. Borrione and W. Paul, editors. Proceedings 13th IFIP Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME'05), Saarbrucken, Germany, October 3-6, 2005. LNCS 3725, pages 345--348. Springer-Verlag, 2005.
Full version available as B. Gebremichael, F.W. Vaandrager and M. Zhang. Formal Models of Guaranteed and Best-Effort Services for Networks on Chip. Technical Report ICIS-R05016, ICIS, Radboud University Nijmegen, March 2005.


Networks on a chip (NoC) are emerging as a scalable, compositional and efficient alternative to existing on-chip interconnects (such as point to point networks or buses). Aethereal is a protocol that has been proposed by Philips to enable both guaranteed and best effort communication in an on-chip packet switching network. We present a formal specification of the Aethereal protocol and its underlying network. All components of the network and their behavior are specified in detail, using the PVS specification language. Using PVS we prove, for an abstract version of our model, absence of deadlock within the Aethereal protocol.

CHARME paper (pdf)
CHARME poster (pdf)
Technical report (pdf)
PVS sources